Recently, research has been actively conducted on a variety of technologies for reducing current consumption of a semiconductor memory device mounted in a portable system such as a mobile phone or notebook computer. In particular, technology for reducing a current consumed in a precharge mode as well as in an active mode is being researched.
FIG. 1 is a block diagram illustrating the configuration of a known semiconductor memory device.
Referring to FIG. 1, the known semiconductor memory device includes a memory cell 11, a local sense amplifier 12, a bit line sense amplifier 13, and an input/output switching unit 14.
The memory cell 11 includes a cell transistor N11 and a cell capacitor C11. The memory cell 11 configured in such a manner stores data DATA in the cell capacitor C11 through the cell transistor N11.
The local sense amplifier 12 includes a plurality of NMOS transistors N12 to N15. The NMOS transistor N12 is coupled between a bit line bar BLB and a first node nd14 and configured to be turned on when an enable signal SG is enabled to a logic high level. The NMOS transistor N13 is coupled between a bit line BL and a second node nd15 and configured to be turned on when the enable signal SG is enabled to a logic high level. The NMOS transistor N14 is coupled between the first node nd14 and a third node nd16 and configured to be turned on when a signal of the bit line BL is at a logic high level. The NMOS transistor N15 is coupled between the second node nd15 and the third node nd16 and configured to be turned on when a signal of the bit line bar BLB is at a logic high level. The threshold voltages Vt of the NMOS transistor N14 and the NMOS transistor N15 are lower by about 100 mV than the threshold voltages of the NMOS transistor N12 and the NMOS transistor N13. The local sense amplifier 12 is enabled in a period where the enable signal SG is enabled and performs an operation of sensing and amplifying a potential difference ΔV between the bit line BL and the bit line bar BLB (hereafter, referred to as a sensing operation). The enable signal SG is enabled to a logic high level in synchronization with an active command, and disabled before the bit line sense amplifier 13 performs a sensing operation.
The bit line sense amplifier 13 is configured to perform a sensing operation when a first power SB is driven to a ground voltage and a second power RTO is driven to an external voltage VDD.
The input/output switching unit 14 includes NMOS transistors N16 and N17, and is configured to transmit data DATA loaded in the bit line BL to an input/output line SIO and transmit data DATAB loaded in the bit line bar BLB to an input/output line bar SIOB, when an output enable signal YI is enabled to a logic high level.
Hereafter, the operation of the known semiconductor memory device will be described. The following descriptions will be divided into a case in which the known semiconductor memory device operates in an active mode and a case in which the known semiconductor memory device operates in a precharge mode.
First, when a word line WL is selected by an active command, charge sharing occurs between the cell capacitor C11 and the bit line BL. A potential difference ΔV occurs between the bit line BL and the bit line bar BLB due to the charge sharing between the bit line BL and the cell capacitor C11. The local sense amplifier 12 performs a sensing operation in a period where the enable signal SG is enabled. The bit line sense amplifier 13 performs a sensing operation when the first power SB is driven to the ground voltage VSS and the second power RTO is driven to the external voltage VDD. Here, the enable signal SG is enabled in synchronization with the active command, and disabled before the bit line sense amplifier 13 performs a sensing operation. When the output enable signal YI is enabled to a logic high level, the NMOS transistors N16 and N17 of the input/output switching unit 14 are turned on to transmit the data DATA loaded in the bit line BL to the input/output line SIO and transmit the data DATAB loaded in the bit line bar BLB to the input/output line bar SIOB.
Then, the first power SB and the second power RTO are driven to a precharge voltage VBLP having a ½ level of the core voltage VCORE by a precharge command. The first power SB and the second power RTO drive the bit line BL and the bit line bar BLB to the precharge voltage VBLP. In the local sense amplifier 12, a microcurrent flows to the ground voltage VSS through the NMOS transistors N14 and N15 having a low threshold voltage Vt. Therefore, since electric charges of the first and second nodes nd14 and nd15 are reduced, a voltage difference between drain and source terminals of the NMOS transistors N12 and N13 increases. Accordingly, a microcurrent is also passed through the NMOS transistors N12 and N13. As a result, in the precharge mode, a leakage current path is formed between the bit line bar BLB and the ground voltage VSS through the NMOS transistors N12 and N14, and a leakage current path is also formed between the bit line BL and the ground voltage VSS through the NMOS transistors N13 and N15. Therefore, the current consumption of the semiconductor memory device increases.